Semiconductor technologies continuously evolve such that leading edge semiconductors have decreased geometries of transistor sizes and decreased voltages for voltage supplies. The smaller transistors are now manufactured with very thin gate oxide material. As a result, the dielectric breakdown voltage for such transistors has decreased. Thus, a decreased voltage supply is both desirable in order to reduce power consumption and necessary in order to avoid damaging the very thin gate oxide material. Also, even if a voltage supply does not immediately damage a transistor, it can be a benefit. A decreased voltage supply will increase the lifetime of the transistors to which it is connected. Meanwhile, other semiconductor products coupled to leading edge semiconductor products still have much higher breakdown voltage devices, and utilize higher supply voltages.
For many years, semiconductor designers have dealt with the problem of translating between various levels of supply voltages. For example, when technology transferred between TTL (Transistor to Transistor Logic) to MOS (Metal Oxide Silicon) technology there was a need for voltage level shifting to be performed between the TTL and MOS technologies. Additionally, as supply voltages gradually decreased from 15 Volts to 5 Volts to 3 Volts, designers created interface circuits which could operate between different voltage systems. However, most of those designs were focused on the issue of being able to just interface between one system operating at one voltage and a second system operating at a different voltage. Such systems typically did not have the problem of coping with breakdown voltages of transistors being threatened by the higher voltage system.
There are many chips and integrated circuits such as memories, memory controllers, and other peripherals that work with leading edge microprocessors. However, such peripherals and memories have not changed their supply voltages or reduced their voltage levels nearly as quickly as microprocessors have. In being able to interface between a peripheral circuit that has a much higher voltage than a leading edge integrated circuit, such as a microprocessor, designers often use a well biasing technique to try to minimize the impact in an integrated circuit of receiving a voltage signal much higher than the supply voltage intended for that integrated circuit. The well bias technique which is used eliminates a charge drain from the output node to an output stage power supply within the circuit. Prior circuits typically dealt with receiving higher voltage levels and using those voltage levels in a system operating at a lower voltage level. However, such systems did not typically worry about or have to compensate for transistor damage due to thin gate oxides. As technologies have evolved, the maximum voltage permitted across a transistor has decreased much faster than the decrease of supply voltages for the output bus. As a result, a need exists for a circuit and method which is able to guarantee the integrity of transistors and transistor gate oxides when interfacing with very high supply voltages at the output bus.